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ST72321xx-Auto Device configuration and ordering information
Doc ID 13829 Rev 1 227/243
21.2 ROM device ordering information and transfer of customer
code
Customer code is made up of the ROM/FASTROM contents and the list of the selected
options (if any). The ROM/FASTROM contents are to be sent on diskette, or by electronic
means, with the S19 hexadecimal file generated by the development tool. All unused bytes
must be set to FFh.
Complete the appended Option list on page 230 to communicate the selected options to
STMicroelectronics and check for regular updates of the option list on the ST website or ask
your ST representative.
Refer to application note AN1635 for information on the counter listing returned by ST after
code has been transferred.
The following Figure 106 and Figure 107 serve as guides for ordering. The
STMicroelectronics Sales Organization will be pleased to provide detailed information on
contractual points.
Caution: The Readout Protection binary value is inverted between ROM and Flash products. The
option byte checksum will differ between ROM and Flash.
- ST72321xx-Auto 1
- Contents 2
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- 1 Description 18
- ST72321xx-Auto Description 19
- 2.1 Package pinout 20
- 2.2 Pin description 22
- 4 Flash program memory 29
- 4.4 ICC interface 30
- Doc ID 13829 Rev 1 31/243 31
- 4.7 Related documentation 32
- 5.1 Introduction 33
- 5.2 Main features 33
- 5.3 CPU registers 33
- 5.3.1 Accumulator (A) 34
- 5.3.3 Program counter (PC) 34
- Interrupt management bits 35
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- 6.1 Introduction 37
- 6.2 Main features 37
- 6.3 Phase locked loop 38
- 6.4 Multi-oscillator (MO) 38
- Crystal/ceramic oscillators 39
- Internal RC oscillator 39
- 6.5.1 Introduction 40
- 6.5.5 Internal watchdog RESET 42
- Doc ID 13829 Rev 1 43/243 43
- Monitoring the V 44
- main supply 44
- 6.6.3 Low power modes 46
- 6.6.4 Interrupts 46
- SICSR description 47
- Application notes 48
- 7 Interrupts 49
- Servicing pending interrupts 50
- Non-maskable sources 51
- Maskable sources 51
- 52/243 Doc ID 13829 Rev 1 52
- HARDWARE PRIORITY 52
- 7.6 External interrupts 57
- Interrupts ST72321xx-Auto 58
- ST72321xx-Auto Interrupts 59
- 8 Power saving modes 62
- 8.3 Wait mode 63
- 8.4.1 Active Halt mode 65
- 8.4.2 Halt mode 67
- Halt mode recommendations 69
- 9 I/O ports 70
- 9.2.2 Output modes 71
- 9.2.3 Alternate functions 71
- 1. The diode to V 72
- ST72321xx-Auto I/O ports 73
- 9.3 I/O port implementation 74
- 9.4 Low power modes 75
- 9.5 Interrupts 75
- 10 Watchdog timer (WDG) 77
- 78/243 Doc ID 13829 Rev 1 78
- 10.5 Low power modes 80
- 10.8 Interrupts 80
- 10.9 Register description 81
- (MCC/RTC) 82
- Low power modes 83
- Interrupts 83
- 12.2 Functional description 88
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- 12.2.8 Input capture function 91
- 92/243 Doc ID 13829 Rev 1 92
- 12.3 ART registers 93
- 13 16-bit timer 98
- 13.3 Functional description 99
- 16-bit timer ST72321xx-Auto 100
- 16-bit read sequence 101
- 13.3.2 External clock 102
- 13.3.3 Input capture 103
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- 13.3.4 Output compare 105
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- Doc ID 13829 Rev 1 107/243 107
- 13.3.6 One Pulse mode 108
- Doc ID 13829 Rev 1 109/243 109
- Procedure 110
- 13.4 Low power modes 112
- 13.5 Interrupts 112
- 13.6 Summary of timer modes 112
- 13.7 16-bit timer registers 113
- ST72321xx-Auto 16-bit timer 115
- 117
- Related documentation 120
- 14.1 Introduction 121
- 14.2 Main features 121
- 14.3 General description 121
- 14.3.1 Functional description 122
- 14.3.3 Master mode operation 124
- 14.3.5 Slave mode operation 125
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- Doc ID 13829 Rev 1 127/243 127
- CPHA = 1 127
- CPHA = 0 127
- 14.5 Error flags 128
- 14.5.4 Single master systems 129
- 14.6 Low power modes 130
- 14.7 Interrupts 130
- 14.8 SPI registers 131
- 15.3 General description 136
- Figure 62. SCI block diagram 137
- 15.4 Functional description 138
- 15.4.2 Transmitter 139
- 15.4.3 Receiver 140
- Doc ID 13829 Rev 1 141/243 141
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- Extended baud rate generation 143
- Parity control 144
- SCI clock tolerance 144
- Clock deviation causes 145
- Noise error causes 145
- 15.5 Low power modes 146
- 15.6 Interrupts 146
- 15.7 SCI registers 147
- 16.3 General description 156
- 16.3.3 SDA/SCL line control 157
- 16.4 Functional description 158
- 16.4.2 Master mode 159
- Slave address transmission 160
- Master receiver 160
- Master transmitter 160
- Error cases 161
- 16.5 Low power modes 163
- 16.6 Interrupts 163
- 16.7 Register description 164
- 16.7.2 I 165
- C status register 1 (SR1) 165
- 16.7.3 I 167
- C status register 2 (SR2) 167
- 16.7.4 I 168
- 16.7.5 I 169
- C data register (DR) 169
- 16.7.6 I 169
- C own address register (OAR1) 169
- 16.7.7 I 170
- C own address register (OAR2) 170
- Table 90. I 171
- 17.1 Introduction 172
- 17.2 Main features 172
- 17.3 Functional description 173
- 17.4 Low power modes 174
- 17.5 Interrupts 174
- 17.6 ADC registers 174
- 17.6.2 Data register (ADCDRH) 175
- 17.6.3 Data register (ADCDRL) 176
- 18 Instruction set 177
- 18.1.1 Inherent 178
- 18.1.2 Immediate 179
- 18.1.3 Direct 179
- 18.1.5 Indirect (short, long) 180
- 18.2 Instruction groups 181
- 18.2.1 Using a prebyte 182
- 19 Electrical characteristics 185
- 19.3 Operating conditions 188
- IT+(LVD) 189
- : Flash devices 192
- Power consumption vs f 192
- 19.5.1 General timings 195
- 19.5.2 External clock source 195
- 19.5.5 PLL characteristics 198
- 19.6 Memory characteristics 199
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- 19.9.1 Asynchronous RESET pin 207
- 208/243 Doc ID 13829 Rev 1 208
- 19.9.2 ICCSEL/V 209
- ICCSEL/V 210
- PROGRAMMING 210
- Doc ID 13829 Rev 1 213/243 213
- 19.11.2 214
- ±5% tolerance 215
- ±2% tolerance 215
- INJ(PIN) 216
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- 19.12.3 ADC accuracy 219
- 20 Package characteristics 220
- 21.1.1 Flash configuration 223
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- 21.3 Development tools 231
- 21.4 ST7 application notes 233
- 22 Known limitations 234
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- 22.1.8 16-bit timer PWM mode 239
- 22.2 All Flash devices 240
- Doc ID 13829 Rev 1 241/243 241
- 23 Revision history 242
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