Auto Page CPX-3600 Especificaciones Pagina 6
- Pagina / 243
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Contents ST72321xx-Auto
6/243 Doc ID 13829 Rev 1
13.7.4 Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 116
13.7.5 Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.7.6 Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 117
13.7.7 Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 117
13.7.8 Output compare 2 high register (OC2HR) . . . . . . . . . . . . . . . . . . . . . . 117
13.7.9 Output compare 2 low register (OC2LR) . . . . . . . . . . . . . . . . . . . . . . . 118
13.7.10 Counter high register (CHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.7.11 Counter low register (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.7.12 Alternate counter high register (ACHR) . . . . . . . . . . . . . . . . . . . . . . . . 118
13.7.13 Alternate counter low register (ACLR) . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.7.14 Input capture 2 high register (IC2HR) . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.7.15 Input capture 2 low register (IC2LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.3.2 Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.3.3 Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.3.4 Master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.3.5 Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.3.6 Slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.5.1 Master mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.5.2 Overrun condition (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.5.3 Write collision error (WCOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.5.4 Single master systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.6.1 Using the SPI to wake up the MCU from Halt mode . . . . . . . . . . . . . . 130
14.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.8 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.8.1 Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.8.2 Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
14.8.3 Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
- ST72321xx-Auto 1
- Contents 2
- Doc ID 13829 Rev 1 3/243 3
- 4/243 Doc ID 13829 Rev 1 4
- Doc ID 13829 Rev 1 5/243 5
- 6/243 Doc ID 13829 Rev 1 6
- Doc ID 13829 Rev 1 7/243 7
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- Doc ID 13829 Rev 1 9/243 9
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- Doc ID 13829 Rev 1 11/243 11
- Doc ID 13829 Rev 1 13/243 13
- 14/243 Doc ID 13829 Rev 1 14
- 16/243 Doc ID 13829 Rev 1 16
- Doc ID 13829 Rev 1 17/243 17
- 1 Description 18
- ST72321xx-Auto Description 19
- 2.1 Package pinout 20
- 2.2 Pin description 22
- 4 Flash program memory 29
- 4.4 ICC interface 30
- Doc ID 13829 Rev 1 31/243 31
- 4.7 Related documentation 32
- 5.1 Introduction 33
- 5.2 Main features 33
- 5.3 CPU registers 33
- 5.3.1 Accumulator (A) 34
- 5.3.3 Program counter (PC) 34
- Interrupt management bits 35
- 36/243 Doc ID 13829 Rev 1 36
- 6.1 Introduction 37
- 6.2 Main features 37
- 6.3 Phase locked loop 38
- 6.4 Multi-oscillator (MO) 38
- Crystal/ceramic oscillators 39
- Internal RC oscillator 39
- 6.5.1 Introduction 40
- 6.5.5 Internal watchdog RESET 42
- Doc ID 13829 Rev 1 43/243 43
- Monitoring the V 44
- main supply 44
- 6.6.3 Low power modes 46
- 6.6.4 Interrupts 46
- SICSR description 47
- Application notes 48
- 7 Interrupts 49
- Servicing pending interrupts 50
- Non-maskable sources 51
- Maskable sources 51
- 52/243 Doc ID 13829 Rev 1 52
- HARDWARE PRIORITY 52
- 7.6 External interrupts 57
- Interrupts ST72321xx-Auto 58
- ST72321xx-Auto Interrupts 59
- 8 Power saving modes 62
- 8.3 Wait mode 63
- 8.4.1 Active Halt mode 65
- 8.4.2 Halt mode 67
- Halt mode recommendations 69
- 9 I/O ports 70
- 9.2.2 Output modes 71
- 9.2.3 Alternate functions 71
- 1. The diode to V 72
- ST72321xx-Auto I/O ports 73
- 9.3 I/O port implementation 74
- 9.4 Low power modes 75
- 9.5 Interrupts 75
- 10 Watchdog timer (WDG) 77
- 78/243 Doc ID 13829 Rev 1 78
- 10.5 Low power modes 80
- 10.8 Interrupts 80
- 10.9 Register description 81
- (MCC/RTC) 82
- Low power modes 83
- Interrupts 83
- 12.2 Functional description 88
- Doc ID 13829 Rev 1 89/243 89
- 90/243 Doc ID 13829 Rev 1 90
- 12.2.8 Input capture function 91
- 92/243 Doc ID 13829 Rev 1 92
- 12.3 ART registers 93
- 13 16-bit timer 98
- 13.3 Functional description 99
- 16-bit timer ST72321xx-Auto 100
- 16-bit read sequence 101
- 13.3.2 External clock 102
- 13.3.3 Input capture 103
- 104/243 Doc ID 13829 Rev 1 104
- 13.3.4 Output compare 105
- 106/243 Doc ID 13829 Rev 1 106
- Doc ID 13829 Rev 1 107/243 107
- 13.3.6 One Pulse mode 108
- Doc ID 13829 Rev 1 109/243 109
- Procedure 110
- 13.4 Low power modes 112
- 13.5 Interrupts 112
- 13.6 Summary of timer modes 112
- 13.7 16-bit timer registers 113
- ST72321xx-Auto 16-bit timer 115
- 117
- Related documentation 120
- 14.1 Introduction 121
- 14.2 Main features 121
- 14.3 General description 121
- 14.3.1 Functional description 122
- 14.3.3 Master mode operation 124
- 14.3.5 Slave mode operation 125
- 126/243 Doc ID 13829 Rev 1 126
- Doc ID 13829 Rev 1 127/243 127
- CPHA = 1 127
- CPHA = 0 127
- 14.5 Error flags 128
- 14.5.4 Single master systems 129
- 14.6 Low power modes 130
- 14.7 Interrupts 130
- 14.8 SPI registers 131
- 15.3 General description 136
- Figure 62. SCI block diagram 137
- 15.4 Functional description 138
- 15.4.2 Transmitter 139
- 15.4.3 Receiver 140
- Doc ID 13829 Rev 1 141/243 141
- 142/243 Doc ID 13829 Rev 1 142
- Extended baud rate generation 143
- Parity control 144
- SCI clock tolerance 144
- Clock deviation causes 145
- Noise error causes 145
- 15.5 Low power modes 146
- 15.6 Interrupts 146
- 15.7 SCI registers 147
- 16.3 General description 156
- 16.3.3 SDA/SCL line control 157
- 16.4 Functional description 158
- 16.4.2 Master mode 159
- Slave address transmission 160
- Master receiver 160
- Master transmitter 160
- Error cases 161
- 16.5 Low power modes 163
- 16.6 Interrupts 163
- 16.7 Register description 164
- 16.7.2 I 165
- C status register 1 (SR1) 165
- 16.7.3 I 167
- C status register 2 (SR2) 167
- 16.7.4 I 168
- 16.7.5 I 169
- C data register (DR) 169
- 16.7.6 I 169
- C own address register (OAR1) 169
- 16.7.7 I 170
- C own address register (OAR2) 170
- Table 90. I 171
- 17.1 Introduction 172
- 17.2 Main features 172
- 17.3 Functional description 173
- 17.4 Low power modes 174
- 17.5 Interrupts 174
- 17.6 ADC registers 174
- 17.6.2 Data register (ADCDRH) 175
- 17.6.3 Data register (ADCDRL) 176
- 18 Instruction set 177
- 18.1.1 Inherent 178
- 18.1.2 Immediate 179
- 18.1.3 Direct 179
- 18.1.5 Indirect (short, long) 180
- 18.2 Instruction groups 181
- 18.2.1 Using a prebyte 182
- 19 Electrical characteristics 185
- 19.3 Operating conditions 188
- IT+(LVD) 189
- : Flash devices 192
- Power consumption vs f 192
- 19.5.1 General timings 195
- 19.5.2 External clock source 195
- 19.5.5 PLL characteristics 198
- 19.6 Memory characteristics 199
- 200/243 Doc ID 13829 Rev 1 200
- 201
- Doc ID 13829 Rev 1 205/243 205
- 206/243 Doc ID 13829 Rev 1 206
- 19.9.1 Asynchronous RESET pin 207
- 208/243 Doc ID 13829 Rev 1 208
- 19.9.2 ICCSEL/V 209
- ICCSEL/V 210
- PROGRAMMING 210
- Doc ID 13829 Rev 1 213/243 213
- 19.11.2 214
- ±5% tolerance 215
- ±2% tolerance 215
- INJ(PIN) 216
- Doc ID 13829 Rev 1 217/243 217
- 218/243 Doc ID 13829 Rev 1 218
- 19.12.3 ADC accuracy 219
- 20 Package characteristics 220
- 21.1.1 Flash configuration 223
- Doc ID 13829 Rev 1 227/243 227
- 230/243 Doc ID 13829 Rev 1 230
- 21.3 Development tools 231
- 21.4 ST7 application notes 233
- 22 Known limitations 234
- Doc ID 13829 Rev 1 235/243 235
- 236/243 Doc ID 13829 Rev 1 236
- Doc ID 13829 Rev 1 237/243 237
- 238/243 Doc ID 13829 Rev 1 238
- 22.1.8 16-bit timer PWM mode 239
- 22.2 All Flash devices 240
- Doc ID 13829 Rev 1 241/243 241
- 23 Revision history 242
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